1. Technical Field
The present invention relates generally to integrated circuits and, in particular, to alternating current (AC) supply noise reduction in a 3D stack with voltage sensing and clock shifting.
2. Description of the Related Art
Supply noise is spatially dependent on the current sources that are used. In general, simultaneous clock switching in synchronous clock systems causes large power supply noise through the power and ground power grids. Such synchronous clock systems may be used, for example, in 3D stacked chips.
Three-dimensional (3D) stacked chips include two or more electronic integrated circuit chips stacked one on top of the other. The chips are connected to each other with chip-to-chip interconnects that could use C4 or other technology, and the chips could include through-Silicon vias (TSVs) to connect from the front side to the back side of the chip. Given the amount of simultaneous clock switching that typically occurs in 3D chips, the reduction of AC noise in 3D chips is particularly of interest.